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64 Mbit SPI Serial Dual I/O Flash
A Microchip Technology Company
SST25VF064C
Data Sheet
Fast-Read Dual I/O (50 MHz)
The Fast-Read Dual I/O (BBH) instruction reduces the total number of input clock cycles, which results
in faster data access. The device is first selected by driving Chip Enable CE# low. Fast-Read Dual I/O
is initiated by executing an 8-bit command (BBH) on SI/SIO 0 , thereafter, the device accepts address
bits A23-A0 and a dummy byte on SI/SIO 0 and SO/SIO 1 . It offers the capability to input address bits
A23-A0 at a rate of two bits per clock. Odd address bits A23 through A1 are input on SIO 1 and even
address bits A22 through A0 are input on SIO 0 , alternately For example the most significant bit is input
first followed by A23/22, A21/A20, and so on. Each bit is latched at the same rising edge of the Serial
Clock (SCK). The input data during the dummy clocks is “don’t care”. However, the SIO 0 and SIO 1 pin
must be in high-impedance prior to the falling edge of the first data output clock.
Following a dummy cycle, the Fast-Read Dual I/O instruction outputs the data starting from the speci-
fied address location on the SIO 1 and SIO 0 lines. SIO 1 outputs, per clock sequence, odd data bits D7,
D5, D3, and D1; and SIO 0 outputs even data bits D6, D4, D2, and D0 per clock edge. CE# must remain
active low for the duration of the Fast-Read Dual I/O instruction cycle. The data output stream is con-
tinuous through all addresses until terminated by a low-to-high transition on CE#.
The internal address pointer will automatically increment until the highest memory address is reached.
Once the highest memory address is reached, the address pointer automatically increments to the
beginning (wraparound) of the address space. For example, once the data from address location
7FFFFFH is read, the next output is from address location 000000H. See Figure 9 for the Fast-Read
Dual I/o sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
MODE 0
Dummy
Cycle
IO, Switches from Input to Output
SIO0
BB
6 4 2 0 6 4 2 0 6 4 2 0
X
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
DOUT
DOUT
DOUT
DOUT
SIO1
7 5 3 1
7 5 3 1
7 5 3 1
X
7 5 3 1
7 5 3 1
7 5 3 1
7 5 3 1 7
MSB
MSB
MSB
MSB
A23-16
A15-8
A7-0
N
N+1
N+2
N+3
1392 F29.0
Figure 9: Fast-Read Dual I/O Sequence
?2011 Silicon Storage Technology, Inc.
15
DS25036A
06/11
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